ANUPLACE: A Synthesis Aware VLSI Placer to Minimize Timing Closure
Santeppa Kambham1 and Krishna Prasad K.S.R2
1ANURAG, DRDO, Kanchanbagh, Hyderabad-500058, India
2ECE Dept, National Institute of Technology, Warangal-506004, India
In Deep Sub Micron (DSM) technologies, circuits fail to meet the timings estimated during synthesis after completion of the layout which is termed as ‘Timing Closure’ problem. This work focuses on the study of reasons for failure of timing closure for a given synthesis solution. It was found that this failure is due to non-adherence of synthesizer’s assumptions during placement. A synthesis aware new placer called ANUPLACE was developed which adheres to assumptions made during synthesis. The new algorithms developed are illustrated with an example. ANUPLACE was applied to a set of standard placement benchmark circuits. There was an average improvement of 53.7% in the Half-Perimeter-Wire-Lengths (HPWL) with an average area penalty of 12.6% of the placed circuits when compared to the results obtained by the existing placement algorithms reported in the literature.