Deep Sub-Micron SRAM Design for DRV Analysis and Low Leakage
Sanjay Kr Singh1, Sampath Kumar2, Arti Noor3, D. S. Chauhan4 & B.K.Kaushik5
1IPEC, Ghaziabad, India.
2J.S.S. Academy of Technical Education, Noida, India.
3Centre for Development of Advance Computing, Noida, India.
4 UTU, Dehradun, India.
5IIT Roorkee, India.
This paper deals with the design opportunities of Static Random Access Memory (SRAM) for lower power consumption and propagation delay. Initially the existing SRAM architectures are investigated, and thereafter a suitable basic 6T SRAM structure is chosen. The key to low power dissipation in the SRAM data path is to reduce the signal swings on the highly capacitive nodes like the bit and data lines. While designing the SRAM, techniques such as circuit partitioning, divide word line and low power layout methodologies are reviewed to minimize the power dissipation.